CMOS technology has evolved such that the computer market has rapidly opened up to a wide range of consumers. Today's multi-media computer uses over 300 MHz microprocessor with 64 MB main memory. In the near future, 1 Gb micro-processor with a 1 GB main memory will become commonplace, which suggests a potentially strong research and development for Giga-Hz and Giga-Byte products, particularly, in products using deep sub-micron technology. Despite the performance, density, and lithographic difficulties, it is even more important in the integrate circuit (IC) marketplace to offer customers a chip which is highly reliable at a competitive cost. To achieve reliability, burn-in testing at the module level is performed to identify weak chips that may be present before they are shipped to a customer. Defective chips found at module burn-in are routinely discarded since they are not readily repairable by on-chip redundancy replacement configurations. This results in higher module costs and lost chip yield.
In view of this problem, and as a possible solution to resolve it, an improved wafer burn-in testing is described herein. Once a weak chip at the wafer level has been detected, it may be repaired if the number of defective elements are less than the number of available redundant repair circuits.
Presently, wafer burn-in methodology applies a static burn-in condition. This is accomplished by accelerating the rate at which marginally functioning cells will fail with time. Practitioners in the art will fully realize that reliability fails have a propensity of occurring over a period of time. There are a number of failures that occur the first time a chip is powered-up. However, there is, additionally, a number of failures occurring subsequently as time passes by. The goal is to ship only chips where, ideally, little likelihood exists of additional fails showing up. Since this may easily take days of power-up operation before the number of failures stabilizes, various methods have been implemented to accelerate this process. One of most commonly used approaches to accelerate this process is to apply a voltage which is 1.5.times. higher the normal power supply voltage. However, because of process parameter variation in the fabrication of the chip, using 1.5.times. voltage to a chip can either cause over burn-in or under burn-in. With over burn-in, a reliable chip is destroyed; with under burn-in, a chip which is not reliable may be shipped.
The goal of wafer burn-in is to guarantee chip reliability, without destroying chips and reducing in the process manufacturing yield. It is difficult to realize this goal when a static burn-in condition (1.5.times. voltage) is provided for all chips at burn-in, unless the chip is over designed, in which instance chip performance is sacrificed. What is needed is a way of applying the best level of burn-in voltage at all times during testing. In the design of a chip, there exists a range of variables which must be taken into account and balanced against each other. These variables include wafer yield and key chip performance parameters such as speed, access time, and power dissipation. This collection of variables define what is referred to as the design space. Clearly, various trade-offs exist between getting the best performance versus an optimum wafer yield versus reliability. Traditionally, the very best possible performance is sacrificed for wafer yield and reliability so that the cost per chip is kept low. A large part of this trade-off involves using a lower internal voltage supply for better burn-in and selecting reliability over keeping the internal voltage supply high for better performance.
FIG. 1 shows an example that illustrates some drawbacks found in conventional static burn-in methods applicable to memory chips. Pass gate 100 couples an input to an output terminal, the output terminal being coupled to a load capacitance C 110. The resistance of the pass gate is R. The time constant t from input to output is therefore R.times.C. It is assumed that the nominal gate voltage (Vg) of the transfer gate is 3.3V and nominal oxide thickness (Tox) of pass gate 100 is 6.2 mn, applicable to case (a). The reliability parameter is defined as the electric field applied to the oxide of pass gate 100, i.e., Vg/Tox=5.3 MV/cm. However, because of process deviations, Tox may vary between 6.5 nm and 5.8 mn, and Vg may vary depending on the chip between 3.15V and 3.45V, as shown in cases (b) and (c). In case (b), the resistance R of pass gate 100 is increased, because Vg is lower and Tox is thicker than the nominal case (a). This, in turn, reduces the transfer speed .DELTA.t by 2 ns. In case (c), t is improved by 2 ns, because of a lower R due to a higher Vg and a thinner Tox. However, the electric field oxide stress increases to 6.1 MV/cm, which is likely to destroy pass gate 100 during burn-in when the Vg voltage is boosted to 1.5.times.Vg for acceleration of the stress at high temperatures. It is desirable to allow the nominal value of Vg to shift towards a greater performance, as in case (b), if the test methodology were to capture the chips at a high reliability. Similarly, it is also preferable to shift towards greater reliability, as in case (c), if the test methodology were to capture those chips at a lower reliability.
Ideally, it is highly advantageous to dynamically adjust operating conditions during burn-in. Present burn-in setups are not capable of providing feedback from existing burn-in conditions and from chip operation. Such a situation requires to be supported by appropriate on-chip circuitry to analyze the chip response during burn-in test in real time.